Random number generators are well-known in the art. One conventional random number generator 100, illustrated in block form in FIG. 1, employs a linear feedback shift register (LFSR) circuit 101. Referring to FIG. 1, it can be seen that the LFSR circuit 101 illustrated therein holds sixteen bits, denoted (from least significant to most significant) as b.sub.1 through b.sub.16. In response to transitions of a periodic clock signal SYSCLK provided at a clock input of the LFSR circuit 101, the bits held in the LFSR are shifted right. During the shift right, a "feedback" bit (designated in FIG. 1 as b.sub.f) replaces the most significant bit (b.sub.16) and the least significant bit (b.sub.1) is discarded. When a random number is needed (e.g., by a processor), the bits then in the LFSR circuit 101 are read, via a sixteen bit local bus 104, as the random number.
As is well-known in the art, the random property of the bit values in the LFSR circuit 101 is due to tap circuitry 102 used to generate the feedback bit b.sub.f. That is, particular ones of the bits held in the LFSR circuit 101 are provided to, and are combined by, combinatorial logic circuitry 106 (e.g., XOR circuitry) to determine the value of the feedback bit b.sub.f. In the example of FIG. 1, bits b.sub.15 and b.sub.3 are combined to determine the value of the feedback bit b.sub.f. Also, although not shown in FIG. 1, the combinatorial logic circuitry may also combine the unstable outputs of ring oscillators in order to further randomize the random number sequence.
However, a problem with the conventional random number generator 100 of FIG. 1 is that a sequence of numbers read from the LFSR 101 will not be sufficiently random unless enough SYSCLK periods have passed between each read from the LFSR circuit 101.